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34com/80seg driver & controller for dot matrix lcd S6A0074 1 introduction S6A0074 is a dot matrix lcd driver & controller lsi which is fabricated by low power cmos technology. it can display 1, 2, or 4 lines with 5 x 8 or 6 x 8 dots format. functions character type dot matrix lcd dri ver & controller internal driver: 34 common and 80 segment signal output easy interface with 4 - bit or 8 - bit mpu clock synchronized serial interface 5 x 8 dots matrix possible 6 x 8 dots matrix possible bi - directional shift function all character reverse display display shift per line voltage converter for lcd drive voltage: 13v max (2 times/3 times) various instruction functions automatic power on rese t features internal memory - character generator rom (cgrom): 9,600 bits (240 characters x 5 x 8 dot) - character generator ram (cgram): 64 x 8 bits (8 characters x 5 x 8 dot) - segment icon ram (segram): 16 x 8 bits (96 i cons max.) - display data ram (ddram): 80 x 8 bits (80 characters max.) low power operation - power supply voltage range: 2.7 - 5.5v (v dd ) - lcd drive voltage range: 3.0 - 13.0v (v dd - v5) c mos process programmable duty cycle: 1/17, 1/33 internal oscillator with an external resistor low power consumption bare ch ip available
S6A0074 34com/80seg driver & controller for dot matrix lcd 2 programmable duty cy cles 5 - dot font width display line duty ratio single chip operation numbers displayable characters possible icons 1 1/17 1 line of 32 characters 80 2 1/33 2 lines of 32 characters 80 4 1/33 4 lines of 16 characters 8 0 6 - dot font width display line duty ratio single chip operation numbers displayable characters possible icons 1 1/17 1 line of 26 characters 78 2 1/33 2 lines of 26 characters 78 4 1/33 4 lines of 13 characters 78
34com/80seg driver & controller for dot matrix lcd S6A0074 3 block diagram power on reset (por) system interface serial 4-bit 8-bit instruction register (ir) instruction decoder address counter display data ram (ddram) 80 x 8-bit timing generator oscillator osc1 osc2 ie data register (dr) busy flag segment ram (segram) 16 bytes character generator ram (cgram) 64 bytes character generator rom (cgrom) 9600 bits cursor and blink controller 80-bit shift register 80-bit latch circuit segment driver 34-bit shift register common driver com0- com33 com1- com80 parallel/serial converter and smooth scroll circuit lcd driver voltage selector v1 - v5 input/ output buffer voltage converter reset im rs/cs e/sclk rw/sid db4-db7 db3-db1 db0-sod vci c1 c2 v5out2 v5out3 vdd gnd(vss) 8 7 8 8 8 3 7 8 8 7 8 7 5/6 5
S6A0074 34com/80seg driver & controller for dot matrix lcd 4 pad configuration seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 com9 com10 com11 com12 com13 com14 com15 com16 com25 com26 com27 com28 com29 com30 com31 com32 com33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 chip size: 6450 x 4870 pad size: 100 100 unit : m m x S6A0074 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 v dd osc2 osc1 reset im ie v ss1 rs/cs rw/sid e/sclk db0/sod db1 db2 db3 db4 db5 db6 db7 vci c2 c1 v ss2 v5out2 v5out3 v5 v4 v3 v2 v1 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 com0 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 com21 com22 com23 com24 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 (0, 0) y
34com/80seg driver & controller for dot matrix lcd S6A0074 5 pad center coordinat es table 1. pad location pad no. pad name coordinate pad no. pad name coordinate pad no. pad name coordinate x y x y x y 1 seg56 - 2475 - 2269 32 com15 1512 - 2269 63 c1 305 9 722 2 seg57 - 2350 - 2269 33 com16 1637 - 2269 64 vss2 3059 847 3 seg58 - 2225 - 2269 34 com25 1762 - 2269 65 v5out2 3059 972 4 seg59 - 2100 - 2269 35 com26 1887 - 2269 66 v5out3 3059 1097 5 seg60 - 1975 - 2269 36 com27 2012 - 2269 67 v5 3059 1222 6 seg61 - 1850 - 2269 37 com28 2137 - 2269 68 v4 3059 1347 7 seg62 - 1725 - 2269 38 com29 2262 - 2269 69 v3 3059 1472 8 seg63 - 1600 - 2269 39 com30 2387 - 2269 70 v2 3059 1597 9 seg64 - 1475 - 2269 40 com31 2512 - 2269 71 v1 3059 1722 10 seg65 - 1350 - 2269 41 com32 2637 - 2269 72 com24 2762 2269 11 seg66 - 1225 - 2269 42 com33 2762 - 2269 73 com23 2637 2269 12 seg67 - 1100 - 2269 43 vdd 3059 - 1778 74 com22 2512 2269 13 seg68 - 975 - 2269 44 osc2 3059 - 1653 75 com21 2387 2269 14 seg69 - 850 - 2269 45 osc1 3059 - 1528 76 com20 2262 2269 15 seg70 - 725 - 2269 46 reset 3059 - 1403 77 com19 2137 2269 16 seg71 - 600 - 2269 47 im 3059 - 1278 78 com18 2012 2269 17 seg72 - 425 - 2269 48 ie 3059 - 1153 79 com17 1887 2269 18 seg73 - 350 - 2269 49 vss1 3059 - 1028 80 com8 1762 2269 19 seg74 - 225 - 2269 50 rs/cs 3059 - 903 81 com7 1637 2269 20 seg75 - 100 - 2269 51 rw/sid 3059 - 778 82 com6 1512 2269 21 seg76 24 - 2269 52 e/sclk 3059 - 653 83 com5 1387 2269 22 seg77 149 - 2269 53 db0/sod 3059 - 528 84 com4 1262 2269 23 seg78 274 - 2269 54 db1 3059 - 403 85 com3 1 137 2269 24 seg79 399 - 2269 55 db2 3059 - 278 86 com2 1012 2269 25 seg80 524 - 2269 56 db3 3059 - 153 87 com1 887 2269 26 com9 762 - 2269 57 db4 3059 - 28 88 com0 762 2269 27 com10 887 - 2269 58 db5 3059 97 89 seg1 524 2269 28 com11 1012 - 2269 59 db6 3059 2 22 90 seg2 399 2269 29 com12 1137 - 2269 60 db7 3059 347 91 seg3 274 2269 30 com13 1262 - 2269 61 vci 3059 472 92 seg4 149 2269 31 com14 1387 - 2269 62 c2 3059 597 93 seg5 24 2269
S6A0074 34com/80seg driver & controller for dot matrix lcd 6 table 1. pad location (continued) pad no. pad name coordinate pad no. pad name coordinate pad no. pad name coordinate x y x y x y 94 seg6 - 100 2269 127 seg39 - 3059 187 95 seg7 - 225 2269 128 seg40 - 3059 62 96 seg8 - 350 2269 129 seg41 - 3059 - 62 97 seg9 - 475 2269 130 seg42 - 3059 - 187 98 seg10 - 600 2269 131 seg43 - 3059 - 312 99 seg11 - 725 2269 132 seg44 - 3059 - 437 100 seg12 - 850 2269 133 seg45 - 3059 - 562 101 seg13 - 975 2269 134 seg46 - 3059 - 687 102 seg14 - 1100 2269 135 seg47 - 3059 - 812 103 seg15 - 1225 2269 136 seg48 - 3059 - 937 104 seg16 - 1350 2269 137 seg49 - 3059 - 1062 105 seg17 - 1475 2269 138 seg50 - 3059 - 1187 106 seg18 - 1600 2269 139 seg51 - 3059 - 1312 107 seg19 - 1725 2269 140 seg52 - 3059 - 1437 108 seg20 - 1850 2269 141 seg53 - 3059 - 1562 109 seg21 - 1975 2269 142 seg54 - 3059 - 1687 110 seg22 - 2100 2269 143 seg55 - 3059 - 1812 111 seg23 - 2225 2269 112 seg24 - 2350 2269 113 seg25 - 2475 2269 114 seg26 - 3059 1812 115 seg27 - 3059 1687 116 seg28 - 3059 1562 117 seg29 - 3059 1437 118 seg30 - 3059 1312 119 seg31 - 3059 1187 120 seg32 - 3059 1062 121 seg33 - 3059 937 122 seg34 - 3059 812 123 seg35 - 3059 687 124 seg36 - 3059 562 125 seg37 - 3059 437 126 seg38 - 3059 312
34com/80seg driver & controller for dot matrix lcd S6A0074 7 pad description table 2. pad description pad (no) input/ output name description interface vdd (43) - power supply for logical circuit(+3v,+5v) power supply vss1, vss2 (49, 64) 0v(gnd) v1 - v5 (71 - 67) bias voltage level for lcd driving. vci (61) input input voltage to the voltage converter to generate lcd drive voltage (vci = 2.5 - 4.5v). seg1 ? seg80 (89 - 143, 1 - 25) output segment output segment signal output for lcd drive. lcd com0 ? com33 (72 - 8 8, 26 - 42) output common output common signal output for lcd drive. lcd osc1, osc2 (45, 44) input (osc1), output (osc2) oscillator when use internal oscillator, connect external rf resistor. if external clock is used, connect it to osc1. external resistor /oscillator (osc1) c1, c2 (63, 62) input external capacitance input to use the voltage converter (2 times/3 times), these pins must be connected to the external capacitance. external capacitance reset (46) input reset pin initialized to low - ie (48) input select pin of instruction set when ie = "high", instruction set is selected as table 6. when ie = "low", instruction set is selected as table 10. - v5out2 (65) output two times converter output the value of vci is converted two times. to use three times converter, the same capacitance as that of c1 - c2 should be connected here. v5 capacitance v5out3 (66) three times converter output the value of vci is converted three times. v5 im (47) input interface mode selection select interface mode with th e mpu. when im = "low" : serial mode, when im = "high" : 4 - bit/8 - bit bus mode. -
S6A0074 34com/80seg driver & controller for dot matrix lcd 8 table 2. pad description (continued) pad (no) input/ output name description interface rs/cs (50) input register elect/ chip select when bus mode, used as register selecti on input. when rs/cs = "high", data register is selected. when rs/cs = "low", instruction register is selected. when serial mode, used as chip selection input. when rs/cs = "low", selected. when rs/cs = "high", not selected. (low access enable) mpu rw /sid (51) input read/write/serial input data when bus mode, used as read/write selection input. when rw/sid = "high", read operation. when rw/sid = "low", write operation. when serial mode, used for data input pin. mpu e/sclk (49) input read/write ena ble/serial clock when bus mode, used as read/write enable signal. when serial mode, used as serial clock input pin. mpu db0/sod (53) input. - output/ output data bus 0 bit/ serial output data when 8 - bit bus mode, used as lowest bi - directional data bit. dur ing 4 - bit bus mode, open this pin. when serial mode, used as serial data output pin. if not in read operation, open this pin. mpu db1 - db3 (54 - 56) input. output data bus 1 - 7 when 8 - bit bus mode, used as low order bi - directional data bus. during 4 - bit bus mode or serial mode, open these pins. mpu db4 - db7 (57 - 60) when 8 - bit bus mode, used as high order bi - directional data bus. in case of 4 - bit bus mode, used as both high and low order. db7 used for busy flag output. during serial mode, open these p ins. mpu
34com/80seg driver & controller for dot matrix lcd S6A0074 9 function description system interface this chip has all three kinds interface type with mpu: serial, 4 - bit bus and 8 - bit bus. serial and bus (4 - bit/8 - bit) is selected by im input, and 4 - bit bus and 8 - bit bus is selected by dl bit in the instru ction register. during read or write operation, two 8 - bit registers are used. one is data register (dr), the other is instruction register (ir). the data register (dr) is used as temporary data storage place for being written into or read from ddram/cgram/ segram, target ram is selected by ram address setting instruction. each internal operation, reading from or writing into ram, is done automatically. so to speak, after mpu reads dr data, the data in the next ddram/cgram/segram address is transferred into dr automatically. also after mpu writes data to dr, the data in dr is transferred into ddram/cgram/segram automatically. the instruction register (ir) is used only to store instruction code transferred from mpu. mpu cannot use it to read instruction data. to select register, use rs/cs input pin in 4 - bit/8 - bit bus mode (im = "high") or rs bit in serial mode (im = "low"). rs r/w operation 0 0 instruction write operation (mpu writes instruction code into ir) 0 1 read busy flag (db7) and address counter (db0 - db6) 1 0 data write operation (mpu writes data into dr) 1 1 data read operation (mpu reads data from dr) busy flag (bf) when bf = "high", it indicates that the internal operation is being processed. so during this time the next instruction cannot be accepted. bf can be read, when rs = low and r/w = high (read instruction operation), through db7 before executing the next instruction, be sure that bf is not high.
S6A0074 34com/80seg driver & controller for dot matrix lcd 10 display data ram (dd ram) ddram stores display data of maximum 80 x 8 bits (80 characters) . ddram address is set in the address counter (ac) as a hexadecimal number. (refer to figure 1.) ac6 ac5 ac4 ac3 ac2 ac1 ac0 msb lsb figure 1. ddram address display of 5 - dot font width character 5 - dot 1 - line display in case of 1 - line display with 5 - dot font, the add ress range of ddram is 00h - 4fh (refer to figure 2). display position ddram address com9 com16 seg80 S6A0074 S6A0074 00 01 02 03 04 1 2 3 4 5 com1 com8 seg1 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 0f 16 10 11 12 17 18 19 20 13 14 15 16 21 22 23 24 17 18 25 26 19 1a 1b 1c 27 28 29 30 1d 1e 31 32 1f com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 0f 16 11 12 17 18 19 20 13 14 15 16 21 22 23 24 17 18 25 26 19 1a 1b 1c 27 28 29 30 1d 1e 31 32 1f seg80 seg1 10 20 (after shift left) com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 16 11 12 17 18 19 20 13 14 15 16 21 22 23 24 17 18 25 26 19 1a 1b 1c 27 28 29 30 1d 1e 31 32 (after shift right) 4f 00 0f 10 figure 2. 1 - line x 32 ch. display
34com/80seg driver & controller for dot matrix lcd S6A0074 11 5 - dot 2 - line display in case of 2 - line display with 5 - dot font, the address range of ddram is 00h - 27h, 40h - 67h (refer to figure 3). display position ddram address com9 com16 seg80 S6A0074 S6A0074 00 01 02 03 04 1 2 3 4 5 com1 com8 seg1 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 0f 16 10 11 12 17 18 19 20 13 14 15 16 21 22 23 24 17 18 25 26 19 1a 1b 1c 27 28 29 30 1d 1e 31 32 1f com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 0f 16 11 12 17 18 19 20 13 14 15 16 21 22 23 24 17 18 25 26 19 1a 1b 1c 27 28 29 30 1d 1e 31 32 1f seg80 seg1 10 20 (after shift left) com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 16 11 12 17 18 19 20 13 14 15 16 21 22 23 24 17 18 25 26 19 1a 1b 1c 27 28 29 30 1d 1e 31 32 (after shift right) 27 00 0f 10 com25 com32 40 41 42 43 44 com17 com24 4b 4c 4d 45 46 47 48 49 4a 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f com25 com32 com17 com24 41 42 43 44 4b 4c 4d 45 46 47 48 49 4a 4e 4f 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 50 60 com25 com32 com17 com24 41 42 43 44 4b 4c 4d 45 46 47 48 49 4a 4e 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 67 40 4f 50 figure 3. 2 - line x 32ch. display (5 - dot font width)
S6A0074 34com/80seg driver & controller for dot matrix lcd 12 5 - dot 4 - line display in case of 4 - line display with 5 - dot font, the address range of ddarm is 00h - 13h, 20h - 33h, 40h - 53h, 60h - 73h. (refer to figure 4) seg1 display position ddram address com9 com16 seg80 S6A0074 (after shift left) 40 41 42 43 44 com17 com24 4b 4c 4d 45 46 47 48 49 4a 4e 4f com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 0d 10 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 0f 16 (after shift right) 21 22 23 24 25 26 27 28 com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 16 2d 2e 2b 2c 2a 29 00 33 20 00 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 0f 16 com25 com32 41 42 43 44 com17 com24 4b 4c 4d 50 45 46 47 48 49 4a 4e 4f 61 62 63 64 65 66 67 68 6f 70 com25 com32 6d 6e 6b 6c 6a 69 13 41 42 43 44 com17 com24 4b 4c 4d 45 46 47 48 49 4a 4e 53 40 61 62 63 64 65 66 67 68 com25 com32 6d 6e 6b 6c 6a 69 73 60 21 22 23 24 25 26 27 28 2f 30 2d 2e 2b 2c 2a 29 61 62 63 64 65 66 67 68 6f 6d 6e 6b 6c 6a 69 60 21 22 23 24 25 26 27 28 2f 2d 2e 2b 2c 2a 29 20 figure 4. 4 - line x 16ch. display (5 - dot font width)
34com/80seg driver & controller for dot matrix lcd S6A0074 13 display of 6 - dot font width character when this device is used in 6 - dot font width mode, seg79 and seg80 must be open 6 - dot 1 - line display in case of 1 - line display with 6 - dot font, the address range of ddram is 00h - 4fh. (refer to figure 5) display position ddram address com9 com16 seg78 S6A0074 S6A0074 00 01 02 03 04 1 2 3 4 5 com1 com8 seg1 0b 0c 6 7 8 9 10 11 12 13 05 06 07 08 09 0a 10 11 12 17 18 19 20 13 14 15 16 21 22 23 24 17 18 25 com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 0d 6 7 8 9 10 11 12 13 05 06 07 08 09 0a 11 12 17 18 19 20 13 14 15 16 21 22 23 24 17 18 25 26 19 1a seg78 seg1 (after shift left) com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 6 7 8 9 10 11 12 13 05 06 07 08 09 0a 11 12 17 18 19 20 13 14 15 16 21 22 23 24 17 18 25 26 (after shift right) 4f 00 0f 10 0d 0e 0f 14 15 16 19 26 0e 0f 14 15 16 10 0e 14 15 16 0c 0d figure 5. 1 - line x 26ch. display
S6A0074 34com/80seg driver & controller for dot matrix lcd 14 6 - dot 2 - line display in case of 2 - line display with 6 - dot font, the address range of ddram is 00h - 27h, 40h - 67h (refer to figure 6). display position ddram address com9 com16 seg78 S6A0074 S6A0074 00 01 02 03 04 1 2 3 4 5 com1 com8 seg1 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 0f 16 10 11 12 17 18 19 20 13 14 15 16 21 22 23 24 17 18 25 26 19 com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 0f 16 11 12 17 18 19 20 13 14 15 16 21 22 23 24 17 18 25 26 19 1a seg78 seg1 10 (after shift left) com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 16 11 12 17 18 19 20 13 14 15 16 21 22 23 24 17 18 25 26 (after shift right) 27 00 0f 10 com25 com32 40 41 42 43 44 com17 com24 4b 4c 4d 45 46 47 48 49 4a 4e 4f 50 51 52 53 54 55 56 57 58 59 com25 com32 com17 com24 41 42 43 44 4b 4c 4d 45 46 47 48 49 4a 4e 4f 51 52 53 54 55 56 57 58 59 5a 50 com25 com32 com17 com24 41 42 43 44 4b 4c 4d 45 46 47 48 49 4a 4e 51 52 53 54 55 56 57 58 67 40 4f 50 figure 6. 2 - line x 26h. display (6 - dot font width)
34com/80seg driver & controller for dot matrix lcd S6A0074 15 6 - dot 4 - line display in case of 4 - line display with 6 - dot font, the address range of ddarm is 00h - 13h, 20h - 33h, 40h - 53h, 60h - 73h (refer to figure 7). seg1 display position ddram address com9 com16 seg78 S6A0074 (after shift left) 40 41 42 43 44 com17 com24 4b 4c 45 46 47 48 49 4a com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 0d 6 7 8 9 10 11 12 13 05 06 07 08 09 0a (after shift right) 21 22 23 24 25 26 27 28 com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 6 7 8 9 10 11 12 13 05 06 07 08 09 0a 2b 2a 29 00 33 20 00 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 6 7 8 9 10 11 12 13 05 06 07 08 09 0a com25 com32 41 42 43 44 com17 com24 4b 4c 4d 45 46 47 48 49 4a 61 62 63 64 65 66 67 68 com25 com32 6d 6b 6c 6a 69 13 41 42 43 44 com17 com24 4b 45 46 47 48 49 4a 53 40 61 62 63 64 65 66 67 68 com25 com32 6b 6a 69 73 60 21 22 23 24 25 26 27 28 2d 2b 2c 2a 29 61 62 63 64 65 66 67 68 6b 6c 6a 69 60 21 22 23 24 25 26 27 28 2b 2c 2a 29 20 figure 7. 4 - line x 13ch. display (6 - dot font width)
S6A0074 34com/80seg driver & controller for dot matrix lcd 16 timing generation ci rcuit timing generation circuit generates clock signals for the internal operations. address counter (ac) address counter (ac) stores ddram/cgram/segram address, transferred from ir. after writing into (reading from) ddram/ cgram/segram, ac is automatically increased (decreased) by 1. when rs = "low" and r/w = "high", ac can be read through db0 - db6 cursor/blink control circuit it controls cursor/blink on/off and black/white inversion at cursor position. lcd driver circuit lc d driver circuit has 34 common and 80 segment signals for lcd driving. data from segram/cgram/cgrom is transferred to 80 - bit segment latch serially, and then it is stored to 80 - bit shift latch. when each com is selected by 34 - bit common register, segment d ata also output through segment driver from 80 - bit segment latch. in case of 1 - line display mode, com0 - com17 have 1/17 duty, and in 2 - line or 4 - line mode, com0 - com33 have 1/33 duty ratio.
34com/80seg driver & controller for dot matrix lcd S6A0074 17 cgrom (character gen erator rom) cgrom has 5 x 8 - dot 240 character p attern. cgram (character gen erator ram) cgram has up to 5 8 dots 8 characters. by writing font data to cgram, user defined character can be used (refer to table 4). 5 8 dots character patter n table 4. relationship between character code (ddram) and character pattern (cgram) 0 1 1 0 0 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 a5 a4 a3 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 character code (ddram data) cgram address cgram data pattern number 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 . . . . . . . 0 0 0 x 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 b1 b0 x 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pattern 1 b1 b0 x 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . pattern 8 . . . . . . . . . . . . . . . . . . . . . . . .
S6A0074 34com/80seg driver & controller for dot matrix lcd 18 6 x 8 dots character pattern 0 1 1 0 0 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 a5 a4 a3 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 character code (ddram data) cgram address cgram data pattern number 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 . . . . . . . 0 0 0 x 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 b1 b0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pattern 1 b1 b0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . pattern 8 . . . . . . . . . . . . . . . . . . . . . . . . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1. when be (blink enable bit) = "high", blink is controlled by b1 and b0 bit. in case of 5 - dot font width, when b1 = "1", enabled dots of p0 - p4 will blink, and when b1 = "0" and b0 = "1", enabled dots in p4 will blink, when b1 = "0" and b0 = "0", blink will not happen. in case of 6 - dot font width, when b1 = "1", enabled dots of p0 - p5 will b link, and when b1 = "0" and b0 = "1", enabled dots of p5 will blink, when b1 = "0" and b0 = "0", blink will not happen. 2. "x": don't care
34com/80seg driver & controller for dot matrix lcd S6A0074 19 segram (segment icon ram) segram has segment control data and segment pattern data. during 1 - line display mode, com 0 (com17) makes the data of segram enable to display icons. when used in 2/4 - line display mode com0 (com33) does that. its higher 2 - bits are blinking control data, and lower 6 - bits are pattern data (refer to table 5 and figure 8). table 5. relationship bet ween segram address and display pattern segram address segram data display pattern 5 - dot font width 6 - dot font width a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 b1 b0 x s1 s2 s3 s4 s5 b1 b0 s1 s2 s3 s4 s5 s6 0 0 0 1 b1 b0 x s6 s7 s8 s9 s10 b1 b0 s7 s8 s9 s10 s11 s12 0 0 1 0 b1 b0 x s11 s12 s13 s14 s15 b1 b0 s13 s14 s15 s16 s17 s18 0 0 1 1 b1 b0 x s16 s17 s18 s19 s20 b1 b0 s19 s20 s21 s22 s23 s24 0 1 0 0 b1 b0 x s21 s22 s23 s24 s25 b1 b0 s25 s26 s27 s28 s29 s30 0 1 0 1 b1 b0 x s26 s27 s28 s29 s30 b1 b0 s31 s32 s33 s34 s35 s36 0 1 1 0 b1 b0 x s31 s32 s33 s34 s35 b1 b0 s37 s38 s39 s40 s41 s42 0 1 1 1 b1 b0 x s36 s37 s38 s39 s40 b1 b0 s43 s44 s45 s46 s47 s48 1 0 0 0 b1 b0 x s41 s42 s43 s44 s45 b1 b0 s49 s50 s51 s52 s53 s54 1 0 0 1 b1 b0 x s46 s47 s48 s49 s50 b1 b0 s55 s56 s57 s58 s59 s60 1 0 1 0 b1 b0 x s51 s52 s53 s54 s55 b1 b0 s61 s62 s63 s64 s65 s66 1 0 1 1 b1 b0 x s56 s57 s58 s59 s60 b1 b0 s67 s68 s69 s70 s71 s72 1 1 0 0 b1 b0 x s61 s62 s63 s64 s65 b1 b0 s73 s74 s75 s76 s77 s78 1 1 0 1 b1 b0 x s66 s67 s68 s69 s70 - - - - - - - - 1 1 1 0 b1 b0 x s71 s72 s73 s74 s75 - - - - - - - - 1 1 1 1 b1 b0 x s76 s77 s78 s79 s80 - - - - - - - - 1. b1, b0: blinking control bit control bit blinking port be b1 b0 5 - dot font width 6 - dot font width 0 x x no blink no blink 1 0 0 no blink no blink 1 0 1 d4 d5 1 1 x d4 - d0 d5 - d0 2. s1 - s80: icon pattern on/off in 5 - dot font width s1 - s78: icon pattern on/off in 6 - dot font width 3. "x": don't care
S6A0074 34com/80seg driver & controller for dot matrix lcd 20 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s76 s77 s78 s79 s80 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg76 seg77 seg78 seg79 seg80 5-dot font width (fw = 0) s1 s2 s3 s4 s5 s7 s8 s9 s10 s11 s67 s68 s71 s72 s74 s75 s76 s77 seg1 seg2 seg3 seg4 seg5 seg7 seg8 seg9 seg10 seg11 seg69 seg70 seg71 seg72 seg74 seg75 seg76 seg77 . . . . . . 6-dot font width (fw = 1) s6 seg6 s12 seg12 s73 seg73 s78 seg78 seg67 seg68 s69 s70 s71 s72 s73 s74 s75 seg71 seg72 seg73 seg74 seg75 . . . figure 8. relationship between segram and segment display
34com/80seg driver & controller for dot matrix lcd S6A0074 21 instruction descript ion outline to overcome the speed difference between internal clock of S6A0074 and mpu clock, S6A0074 performs internal operation by storing control information to i r or dr. the internal operation is determined according to the signal from mpu, composed of read/write and data bus. (refer to table 6/10) instruction can be divided largely four kinds; S6A0074 function set instructions (s et display methods, set data length, etc.) address set instructions to internal ram data transfer instructions with internal ram others the address of inter nal ram is automatically increased or decreased by 1. when ie = "high", S6A0074 is operated according to instruction set 1(table 6) and when ie = "low", S6A0074 is operated according to instruction set 2 (table 10). note: during internal operation, busy f lag (db7) is read high. busy flag check must be proceeded the next instruction. busy flag check must be proceeded the next instruction. when an mpu program with busy flag (db7) checking is made, 1/2 fosc (is necessary) for executing the next instruc tion by the falling edge of the ?e? signal after the busy flag (db7) goes to ?low?.
S6A0074 34com/80seg driver & controller for dot matrix lcd 22 instruction descript ion 1 (ie = "high") table 6. instruction set 1 instruction re instruction code description executi on time rs r/w db7 db6 db5 db4 db3 db2 db1 db0 (fosc = 270khz) clear display x 0 0 0 0 0 0 0 0 0 1 write "20h" to ddram. and set ddram address to "00h" from ac. 1.53ms return home 0 0 0 0 0 0 0 0 0 1 x set ddram address to "00h" from ac and return cursor to its original position if shifted. the con tents of ddram are not changed. 1.53ms power down mode 1 0 0 0 0 0 0 0 0 1 pd set power down mode bit. pd = "1": power down mode set, pd = "0": power down mode disable 39 m s entry mode set 0 0 0 0 0 0 0 0 1 i/d s assign cur sor moving direction. i/d = "1": increment, i/d = "0": decrement and display shift enable bit. s = "1": make display shift of the enabled lines by the ds4 - ds1 bits in the shift enable instruction. s = "0": display shift disable 39 m s 1 0 0 0 0 0 0 0 1 1 b/d segment bi - direction function. bid = "0": seg1 ? seg80, bid = "1": seg80 ? seg1. display on/off control 0 0 0 0 0 0 0 1 d c b set display/cursor/blink on/off d = "1" : display on, d = "0" : display off, c = "1" : cursor on, c = "0" : cursor off, b = "1" : blink on, b = "0" : blink off. 39 m s
34com/80seg driver & controller for dot matrix lcd S6A0074 23 table 6. instruction set 1 (continued) inst ruction re instruction code description executi on time rs r/w db7 db6 db5 db4 db3 db2 db1 db0 (fosc = 270khz) extended function set 1 0 0 0 0 0 0 1 fw b/w nw assign font width, black/white inverting of cursor, and 4 - line display mode control bit. fw = "1": 6 - dot font width, fw = "0": 5 - dot font width, b/w = "1": black/white inverting of cursor enable, b/w = "0": black/white inverting of cursor disable nw = "1": 4 - line display mode, nw = " 0": 1 - line or 2 - line display mode. 39 m s cursor or display shift 0 0 0 0 0 0 1 s/c r/l x x cursor or display shift. s/c = "1" : display shift, s/c = "0" : cursor shift, r/l = "1" : shift to right, r/ l = "0" : shift to left. 39 m s shift enable 1 0 0 0 0 0 1 ds4 ds3 ds2 ds1 (when dh = "1") determine the line for display shift ds1 = "1/0": 1st line display shift enable/disable ds2 = "1/0": 2nd line display shift enable/disable ds3 = "1/0": 3rd line display shift enable/disable ds4 = "1/0": 4th line display shift enable/disable. 39 m s scroll enable 1 0 0 0 0 0 1 hs4 hs3 hs2 hs1 (when dh = "0") dete rmine the line for horizontal smooth scroll. hs1 = "1/0": 1st line dot scroll enable/disable hs2 = "1/0": 2nd line dot scroll enable/disable hs3 = "1/0": 3rd line dot scroll enable/disable hs4 = "1/0": 4th line dot scroll enable/disable. 39 m s
S6A0074 34com/80seg driver & controller for dot matrix lcd 24 table 6. instruction set 1 (continued) instruction re instruction code description executi on time rs r/w db7 db6 db5 db4 db3 db2 db1 db0 (fosc = 270khz) function set 0 0 0 0 0 1 dl n re (0) dh rev set interface data length (dl = "1": 8 - bit, dl = "0": 4 - bit), numbers of display line when nw = "0", (n = "1": 2 - line, n = "0" : 1 - line), extension reg ister, re("0"), shift/scroll enable dh = "1": display shift enable dh = "0": dot scroll enable. reverse bit rev = "1": reverse display, rev = "0": normal display. 39 m s 1 0 0 0 0 1 dl n re (1) be 0 set dl, n, re("1") and cgram/segram blink enable (be) be = "1/0": cgram/segram blink enable/disable 39 m s set cgram address 0 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address in address counter. 39 m s set s egram address 1 0 0 0 1 x x ac3 ac2 ac1 ac0 set segram address in address counter. 39 m s set ddram address 0 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address in address counter. 39 m s set scro ll quantity 1 0 0 1 x qc5 qc4 qc3 qc2 qc1 qc0 set the quantity of horizontal dot scroll. 39 m s read busy flag and address x 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 can be known whether during internal operation or not by reading bf . the contents of address counter can also be read. bf = "1": busy state, bf = "0": ready state. 0 m s write data x 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data into internal ram (ddram / cgram / segram). 43 m s read data x 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read data from internal ram (ddram / cgram / segram). 43 m s "x": don?t care
34com/80seg driver & controller for dot matrix lcd S6A0074 25 display clear rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 1 clear all the display dat a by writing "20h" (space code) to all ddram address, and set ddram address to "00h" into ac (address counter). return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. make entry mode increment (i/d = " 1"). return home: (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 1 x return home is cursor return home instruction. set ddram address to "00h" into the address counter. return cursor to its original site and return display to its origin al status, if shifted. contents of ddram does not change. power down mode set: (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 0 0 0 0 0 1 pd power down mode enable bit set instruction. pd = ? high ? , it makes S6A0074 suppress current consumption exc ept the current needed for data storage by executing next three functions. 1. make the output value of all the com / seg ports vdd 2. disable voltage converter to remove the current through the divide resistor of power supply. this instruction can be used as pow er sleep mode. when pd = ? low ? , power down mode becomes disabled. entry mode set : (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 i/d s set the moving direction of cursor and display. i/d: increment/decrement of ddram address (cursor or blink) when i/d = "high", cursor/blink moves to right and ddram address is increased by 1. when i/d = "low", cursor/blink moves to left and ddram address is decreased by 1. - cgram/segram operates the same as ddram, when read from or write to cgram/se gram. when s = "high", after ddram write, the display of enabled line by ds1 - ds4 bits in the shift enable instruction is shifted to the right (i/d = "0") or to the left (i/d = "1"). but it will seem as if the cursor does not move. when s = "low", or ddra m read, or cgram/segram read/write operation, shift of display like this function is not performed.
S6A0074 34com/80seg driver & controller for dot matrix lcd 26 entry mode set : (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 1 bid set the data shift direction of segment in the application set. b i d: data shift direction of segment when b id = " low ", segment data shift direction is set to normal order from seg1 to seg80. when b id = " high ", segment data shift direction is set to reverse from seg80 to seg1. by using this instruction, the efficiency of application board area can be raised. - the bid setting instruction is recommended to be set at the same time level of function set instruction. - db1 bit must be set to ? 1 ? . display on/off control (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 d c b control display/cursor/blink on/off 1 bit register. d: display on/off control bit when d = "high", entire display is turned on. when d = "low", display is turned off, but display data is remained in ddram. c: cursor on/off co ntrol bit when c = "high", cursor is turned on. when c = "low", cursor is disappeared in current display, but i/d register remains its data. b: cursor blink on/off control bit when b = "high", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. if fosc has 270khz frequency, blinking has 370 ms interval. when b = "low", blink is off. extended function set (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 fw b/w nw fw: font width control when fw = "high", display character font width is assigned to 6 - dot and execution time becomes 6/5 times than that of 5 - dot font width. the user font, specified in cgram, is displayed into 6 - dot font width, bit - 5 to bit - 0,including the lef tmost space bit of cgram.(refer to fig - 9) when fw = "low", 5 - dot font width is set. b/w: black/white inversion enable bit when b/w = "high", black/white inversion at the cursor position is set. in this case c/b bit of display on/off control instruction becomes don't care condition. if fosc has frequency of 270khz, inversion has 370 ms intervals. nw: 4 line mode enable bit when nw = "high", 4 line display mode is set. in this case n bit of function set instruction becomes don't care condition.
34com/80seg driver & controller for dot matrix lcd S6A0074 27 s p a c e cgrom characte font (5-dot) 8-bit 6-bit cgrom cgram characte font (6-dot) 8-bit 6-bit cgram figure 9. 6 - dot font width cgrom/cgram cursor or display shift (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 s/c r/l - - without writing or reading of display data, shift right/left cursor position or display. this instr uction is used to correct or search display data (refer to table 7). during 2 - line mode display, cursor moves to the 2nd line after 40th digit of 1st line. when 4 - line mode, cursor moves to the next line, only after every 20th digit of the current line. no te that display shift is performed simultaneously in all the line enabled by ds1 - ds4 in the shift enable instruction. when displayed data is shifted repeatedly, each line shifted individually. when display shift is performed, the contents of address coun ter are not changed. during low power consumption mode, display shift may not be performed normally. table 7. shift patterns according to s/c and r/l bits s/c r/l operation 0 0 shift cursor to the left, address counter is decreased by 1 0 1 shift cursor to the right, address counter is increased by 1 1 0 shift all the display to the left, cursor moves according to the display 1 1 shift all the display to the right, cursor moves according to the display
S6A0074 34com/80seg driver & controller for dot matrix lcd 28 shift/scroll enable (re = 1) (dh = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 hs4 hs3 hs2 hs1 hs: horizontal scroll per line enable this instruction makes valid dot shift by a display line unit. hs1, hs2, hs3 and hs4 indicate each line to be dot scrolled, and each scroll is performed individually in each line. if you want to scroll the line in 1 - line display mode or the 1st line in 2 - line display mode, set hs1 and hs2 to "high". if the 2nd line scroll is needed in 2 - line mode, set hs3 and hs4 to "high". (refer to table 8) (dh = 1) r s r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 ds4 ds3 ds2 ds1 ds: display shift per line enable this instruction selects shifted to be according to each line mode in display shift right/left instruction. ds1, ds2, ds3 and ds4 indicate each line to be shifted, and each shift is performed individually in each line. if ds1 and ds2 is set to ?high? (enable) in 2 line mode, only the first line is shifted and the second line is not shifted. when only ds1 = ?hig h?, only the half of the first line is shifted. if all the ds bits (ds1 to ds4) are set to ?low? (disable), no display is shifted. table 8. relationship between ds and com signal enable bit enabled common signals during shift operation hs 1/ds1 com1 ~ com8 the part of display line that corresponds to enabled common signal can be shifted. hs2/ds2 com9 ~ com16 hs3/ds3 com17 ~ com24 hs4/ds4 com25 ~ com32
34com/80seg driver & controller for dot matrix lcd S6A0074 29 function set (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 dl n re(0 ) - - dl: interface data length control bit when dl = "high", it means 8 - bit bus mode with mpu. when dl = "low", it means 4 - bit bus mode with mpu. so to speak, dl is a signal to select 8 - bit or 4 - bit bus mode. when 4 - bit bus mode, it needs to transfe r 4 - bit data by two times. n: display line number control bit it is variable only when nw bit of extended function set instruction is low. when n = "low", it means 1 - line display mode. when n = "high", 2 - line display mode is set. when nw = "high", n bit is invalid, it means 4 - line mode independent of n bit. re: extended function registers enable bit at this instruction, re must be "low". dh: display shift enable selection bit when dh = ?high?, enable display shift per line. when dh =?low?, enable smooth dot scroll. this bit can be accessed only when ie pin input is ?high?. rev: reverse enable bit when rev = ?high?, all the display data are reversed. i.e., all the white dots become black and black dots become white. when rev =?low?, the display mode set normal display. (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 dl n re(1) be 0 dl: interface data length control bit when dl = "high", it means 8 - bit bus mode with mpu. when dl = "low", it means 4 - bit bus mode with mpu. so to speak, dl is a signal to select 8 - bit or 4 - bit bus mode. when 4 - bit bus mode, it needs to transfer 4 - bit data by two times. n: display line number control bit it is varia ble only when nw bit of extended function set instruction is low. when n = "low", it means 1 - line display mode. when n = "high", 2 - line display mode is set. when nw = "high", n bit is invalid, it means 4 - line mode independent of n bit. re: extended fun ction registers enable bit when re = "high", extended function set registers, segram address set registers, bid bit, hs/ds bits of shift/scroll enable instruction and be bits of function set register can be accessed. be: cgram/segram data blink enable b it if be is "high", it makes user font of cgram and segment of segram blink. the quantity of blink is assigned the highest 2 bit of cgram/segram.
S6A0074 34com/80seg driver & controller for dot matrix lcd 30 set cgram address (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac1 set cgram address to ac. this instruction makes cgram data available from mpu. set segram address (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 x x ac3 ac2 ac1 ac1 set cgram address to ac. this instruction makes cgram data available from mpu. set ddra m address (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac1 set ddram address to ac. this instruction makes ddram data available from mpu. when 1 - line display mode (n = 0, nw = 0), ddram address is from "00h" - "4fh". in 2 - line display mode (n = 1, nw = 0), ddram address in the 1st line is from "00h" - "27h", and ddram address in the 2nd line is from "40h" - "67h". in 4 - line display mode (nw = 1), ddram address is from "00h" - "13h" in the 1st line, from "20h" - "33h" in the 2nd line, from "40h" - "53h" in the 3rd line and from "60h" - "73h" in the 4th line. set scroll quantity (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 x sq5 sq4 sq3 sq2 sq1 sq0 as set sq5 to sq0, horizontal scroll quantity can be controlled in dot units. (refer to table 9).in this case S6A0074 can show hidden areas of ddram by executing smooth scroll from 1 to 48 dots. table 9. scroll quantity according to hds bits sq5 sq4 sq3 sq2 sq1 sq0 function 0 0 0 0 0 0 no shift 0 0 0 0 0 1 shift left b y 1 - dot 0 0 0 0 1 0 shift left by 2 - dot 0 0 0 0 1 1 shift left by 3 - dot : : : : : : : 1 0 1 1 1 1 shift left by 47 - dot 1 1 x x x x shift left by 48 - dot
34com/80seg driver & controller for dot matrix lcd S6A0074 31 read busy flag & address rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac1 this instruction shows whether S6A0074 is in internal operation or not. if the resultant bf is high, it means the internal operation is in progress and you have to wait until bf to be low, and then the next instruction can be performed. in this instru ction you can read also the value of address counter. write data to ram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write binary 8 - bit data to ddram/cgram/segram. the selection of ram from ddram, cgram, or segram, is set by the pre vious address set instruction: ddram address set, cgram address set, segram address set. ram set instruction can also determines the ac direction to ram. after write operation, the address is automatically increased/decreased by 1, according to the entry m ode. read data from ram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read binary 8 - bit data from ddram/cgram/segram. the selection of ram is set by the previous address set instruction. if address set instruction of ram is not perfo rmed before this instruction, the data that read first is invalid, because the direction of ac is not determined. if you read ram data several times without ram address set instruction before read operation, you can get correct ram data from the second, bu t the first data would be incorrect, because there is no time margin to transfer ram data. in case of ddram read operation, cursor shift instruction plays the same role as ddram address set instruction : it also transfer ram data to output data register. a fter read operation address counter is automatically increased/decreased by 1 according to the entry mode. after cgram/segram read operation, display shift may not be executed correctly. - in case of ram write operation, after this ac is increased/decrease d by 1 like read operation. in this time, ac indicates the next address position, but you can read only the previous data by read instruction.
S6A0074 34com/80seg driver & controller for dot matrix lcd 32 instruction descript ion 2 (ie = "low") table 10. instruction set 2 instruction re instruction code descripti on executi on time rs r/w db7 db6 db5 db4 db3 db2 db1 db0 (fosc = 270khz) clear display x 0 0 0 0 0 0 0 0 0 1 write "20h" to ddram. and set ddram address to "00h" from ac. 1.53ms return home x 0 0 0 0 0 0 0 0 1 x set ddram address to "00h" from ac and return cursor to its original position if shifted. the contents of ddram are not changed. 1.53ms entry mode set x 0 0 0 0 0 0 0 1 i/d s assign cursor moving direction. i/d = "1": increment, i/d = "0": decrement. and display shift enable bit. s = "1" : make entire display shift of all lines during ddram write, s = "0": display shift disable 39 m s display on/off control 0 0 0 0 0 0 0 1 d c b set display/cursor/blink on/off d = "1": display on, d = "0": display off, c = "1 ": cursor on, c = "0": cursor off, b = "1": blink on, b = "0": blink off. 39 m s extended function set 1 0 0 0 0 0 0 1 fw b/w nw assign font width, black/white inverting of cursor, and 4 - line display mode control bit. fw = "1": 6 - dot font width, fw = "0": 5 - dot font width, b/w = "1": black/white inverting of cursor enable, b/w = "0": black/white inverting of cursor disable nw = "1": 4 - line display mode, nw = "0": 1 - line or 2 - line display mode 39 m s cursor or display shift 0 0 0 0 0 0 1 s/c r/l x x cursor or display shift. s/c = "1": display shift, s/c = "0": cursor shift, r/l = "1": shift to right, r/l = "0": shi ft to left 39 m s
34com/80seg driver & controller for dot matrix lcd S6A0074 33 table 10. instruction set 2 (continued) instruction re instruction code description executi on time rs r/w db7 db6 db5 db4 db3 db2 db1 db0 (fosc = 270khz) scroll enable 1 0 0 0 0 0 1 hs4 hs3 hs2 hs1 determine the line for horizontal smooth scroll. hs1 = "1/0": 1st line dot scroll enable/disable hs2 = "1/0": 2nd line dot scroll enable/disable hs3 = "1/0": 3rd line dot scroll enable/disable hs4 = "1/0": 4th line dot scroll enable/disable 39 m s function set 0 0 0 0 0 1 dl n re (0) x x set interface data length dl = "1": 8 - bit, dl = "0": 4 - b it numbers of display line when nw = "0", n = "1": 2 - line, n = "0": 1 - line extension register, re("0"), 39 m s 1 0 0 0 0 1 dl n re (1) be 0 set dl, n, re("1") and cgram/segram blink enable (be) be = "1/0": cgram/segram blink enable/disable 39 m s set cgram address 0 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address in address counter. 39 m s set segram address 1 0 0 0 1 x x ac3 ac2 ac1 ac0 set segram address in address counter. 39 m s set ddram address 0 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address in address counter. 39 m s set scroll quantity 1 0 0 1 x sq5 sq4 sq3 sq2 sq1 sq0 set the quantity of horizontal dot scroll. 39 m s read busy flag and address x 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 can be known whether during internal operation or not by reading bf. the contents of address counter can also be read. bf = "1": busy state, bf = "0": ready state. 0 m s
S6A0074 34com/80seg driver & controller for dot matrix lcd 34 table 10. instruction set 2 (continued) instruction re instruction code description executi on time rs r/w db7 db6 db5 db4 db3 db2 db1 db0 (fosc = 270khz) write data x 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data into internal ram (ddram / cgram / segram). 43 m s read data x 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read data from internal ram (ddram / cgram / segram). 43 m s notes: 1. when a n mpu program with busy flag (db7) checking is made, 1/2 fosc (is necessary) for executing the next instruction by the falling edge of the "e" signal after the busy flag (db7) goes to "low" 2. "x" don?t care
34com/80seg driver & controller for dot matrix lcd S6A0074 35 display clear rs r/w db7 db6 db5 db4 db3 db2 d b1 db0 0 0 0 0 0 0 0 0 0 1 clear all the display data by writing "20h" (space code) to all ddram address, and set ddram address to "00h" into ac (address counter). return cursor to the original status, namely, bring the cursor to the left edge on first l ine of the display. and entry mode is set to increment mode (i/d = "1"). return home rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 1 x return home is cursor return home instruction. set ddram address to "00h" into the address counter. return cur sor to its original site and return display to its original status, if shifted. contents of ddram does not change. entry mode set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 i/d s set the moving direction of cursor and display. i/d: increment /decrement of ddram address (cursor or blink) when i/d = "high", cursor/blink moves to right and ddram address is increased by 1. when i/d = "low", cursor/blink moves to left and ddram address is decreased by 1. - cgram/segram operates the same as ddra m, when read from or write to cgram/segram. when s = "high", after ddram write, the entire display of all lines is shifted to the right (i/d = "0") or to the left(i/d = "1"). but it will seem as if the cursor does not move. when s = "low", or ddram read, or cgram/segram read/write operation, shift of entire display is not performed.
S6A0074 34com/80seg driver & controller for dot matrix lcd 36 display on/off control (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 d c b control display/cursor/blink on/off 1 bit register. d: display on/off control bit when d = "high", entire display is turned on. when d = "low", display is turned off, but display data is remained in ddram. c: cursor on/off control bit when c = "high", cursor is turned on. when c = "low", cursor is disappeared in current display , but i/d register remains its data. b: cursor blink on/off control bit when b = "high", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. if fosc has 270khz frequency, blinking has 370 m s interval. when b = "low", blink is off. extended function set ( re = 1 ) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 fw b/w nw fw: font width control when fw = "high", display character font width is assigned to 6 - dot and execution time bec omes 6/5 times than that of 5 - dot font width. the user font, specified in cgram, is displayed into 6 - dot font width, bit - 5 to bit - 0, including the leftmost space bit of cgram (refer to figure 10). when fw = "low", 5 - dot font width is set. b/w: black/white inversion enable bit when b/w = "high", black/white inversion at the cursor position is set. in this case c/b bit of display on/off control instruction becomes don't care condition. if fosc has frequency of 270khz, inversion has 370 ms intervals. nw: 4 line mode enable bit when nw = "high", 4 line display mode is set. in this case n bit of function set instruction becomes don't care condition. s p a c e cgrom characte font (5-dot) 8-bit 6-bit cgrom cgram characte font (6-dot) 8-bit 6-bit cgram figure 10. 6 - dot font width cgrom/cgram
34com/80seg driver & controller for dot matrix lcd S6A0074 37 cursor or display shift (re = 0) rs r/w d b7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 s/c r/l x x without writing or reading of display data, shift right/left cursor position or display. this instruction is used to correct or search display data.(refer to table 7) during 2 - line mode display, curs or moves to the 2nd line after 40th digit of 1st line. when 4 - line mode, cursor moves to the next line, only after every 20th digit of the current line. note that display shift is performed simultaneously in all the line. when displayed data is shifted rep eatedly, each line shifted individually. when display shift is performed, the contents of address counter are not changed. table 11. shift patterns according to s/c and r/l bits s/c r/l operation 0 0 shift cursor to the left, address counter is decreased by 1 0 1 shift cursor to the right, address counter is increased by 1 1 0 shift all the display to the left, cursor moves according to the display 1 1 shift all the display to the right, cursor moves according to the display scroll enable (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 hs4 hs3 hs2 hs1 hs: horizontal scroll per line enable this instruction makes valid dot shift by a display line unit. hs1, hs2, hs3 and hs4 indicate each line to be dot scrolled, and each scroll is perf ormed individually in each line. if you want to scroll the line in 1 - line display mode or the 1st line in 2 - line display mode, set hs1 and hs2 to "high". if the 2nd line scroll is needed in 2 - line mode, set hs3 and hs4 to "high". (refer to table 8)
S6A0074 34com/80seg driver & controller for dot matrix lcd 38 f unction set (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 dl n re(0) x x dl: interface data length control bit when dl = "high", it means 8 - bit bus mode with mpu. when dl = "low", it means 4 - bit bus mode with mpu. so to speak, dl is a sign al to select 8 - bit or 4 - bit bus mode. when 4 - bit bus mode, it needs to transfer 4 - bit data by two times. n: display line number control bit it is variable only when nw bit of extended function set instruction is low. when n = "low", it means 1 - line d isplay mode. when n = "high", 2 - line display mode is set. when nw = "high", n bit is invalid, it means 4 - line mode independent of n bit. re: extended function registers enable bit at this instruction, re must be "low". (re = 1) rs r/w db7 db6 db5 db4 d b3 db2 db1 db0 0 0 0 0 1 dl n re(1) be 0 dl: interface data length control bit when dl = "high", it means 8 - bit bus mode with mpu. when dl = "low", it means 4 - bit bus mode with mpu. so to speak, dl is a signal to select 8 - bit or 4 - bit bus mode. when 4 - bit bus mode, it needs to transfer 4 - bit data by two times. n: display line number control bit it is variable only when nw bit of extended function set instruction is low. when n = "low", it means 1 - line display mode. when n = "high", 2 - line displa y mode is set. when nw = "high", n bit is invalid, it means 4 - line mode independent of n bit. re: extended function registers enable bit when re = "high", extended function set registers, segram address set registers, hs bits of scroll enable instructi on and be bits of function set register can be accessed. be: cgram/segram data blink enable bit if be is "high", it makes user font of cgram and segment of segram blink. the quantity of blink is assigned the highest 2 bit of cgram/segram.
34com/80seg driver & controller for dot matrix lcd S6A0074 39 set cgram ad dress (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address to ac. this instruction makes cgram data available from mpu. set segram address (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 x x ac3 ac2 a c1 ac0 set segram address to ac. this instruction makes segram data available from mpu. set ddram address (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 1 x ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address to ac. this instruction makes ddram data avail able from mpu. when 1 - line display mode (n = 0, nw = 0), ddram address is from "00h" to "4fh". in 2 - line display mode (n = 1, nw = 0), ddram address in the 1st line is from "00h" to "27h", and ddram address in the 2nd line is from "40h" to "67h". in 4 - lin e display mode (nw = 1), ddram address is from "00h" to "13h" in the 1st line, from "20h" to "33h" in the 2nd line, from "40h" to "53h" in the 3rd line and from "60h" to "73h" in the 4th line. set scroll quantity (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 x sq5 sq4 sq3 aq2 sq1 sq0 as set sq5 to sq0, horizontal scroll quantity can be controlled in dot units. (refer to table 12). in this case S6A0074 execute dot smooth scroll from 1 to 48 dots. table 12. scroll quantity according to hds bits sq5 sq4 sq3 sq2 sq1 sq0 function 0 0 0 0 0 0 no shift 0 0 0 0 0 1 shift left by 1 - dot 0 0 0 0 1 0 shift left by 2 - dot 0 0 0 0 1 1 shift left by 3 - dot : : : : : : : 1 0 1 1 1 1 shift left by 47 - dot 1 1 x x x x shift left by 48 - dot
S6A0074 34com/80seg driver & controller for dot matrix lcd 40 read busy flag & add ress rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 this instruction shows whether S6A0074 is in internal operation or not. if the resultant bf is high, it means the internal operation is in progress and you have to wait until bf to be low, and then the next instruction can be performed. in this instruction you can read also the value of address counter. write data to ram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write binary 8 - bit data to ddram/cgram/ segram. the selection of ram from ddram, cgram, or segram, is set by the previous address set instruction : ddram address set, cgram address set, segram address set. ram set instruction can also determines the ac direction to ram. after write operation, th e address is automatically increased/decreased by 1, according to the entry mode. read data from ram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read binary 8 - bit data from ddram/cgram/segram. the selection of ram is set by the pre vious address set instruction. if address set instruction of ram is not performed before this instruction, the data that read first is invalid, because the direction of ac is not determined. if you read ram data several times without ram address set instru ction before read operation, you can get correct ram data from the second, but the first data would be incorrect, because there is no time margin to transfer ram data. in case of ddram read operation, cursor shift instruction plays the same role as ddram a ddress set instruction : it also transfer ram data to output data register. after read operation address counter is automatically increased/decreased by 1 according to the entry mode. after cgram/segram read operation, display shift may not be executed cor rectly. - in case of ram write operation, after this ac is increased/decreased by 1 like read operation. in this time, ac indicates the next address position, but you can read only the previous data by read instruction.
34com/80seg driver & controller for dot matrix lcd S6A0074 41 interface with mpu S6A0074 can t ransfer data in bus mode (4 - bit or 8 - bit) or serial mode with mpu. so you can use any type 4 or 8 - bit mpu. in case of 4 - bit bus mode, data transfer is performed by two times to transfer 1 byte data. when interfacing data length are 4 - bit, only 4 ports, from db4 - db7, are used as data bus. at first higher 4 - bit (in case of 8 - bit bus mode, the contents of db4 - db7) are transferred, and then lower 4 - bit (in case of 8 - bit bus mode, the contents of db0 - db3) are transferred . so transfer is performed by two times. busy flag outputs "high" after the second transfer are ended. when interfacing data length are 8 - bit, transfer is performed at a time through 8 ports, from db0 - db7. if im is set to "low", serial transfer mode is set.
S6A0074 34com/80seg driver & controller for dot matrix lcd 42 interface with mpu i n bus mode interface with 8 - bit mpu if 8 - bits mpu is used, S6A0074 can connect directly with that. in this case, port e, rs, r/w and db0 to db7 need to interface eac h other. example of timing sequence is shown below. rs r/w e internal signal db7 data busy busy no busy data internal operation instruction busy flag check busy flag check busy flag check instruction figure 11. example of 8 - bit bus mode timing sequence interface with 4 - bit mpu if 4 - bit mpu is used, S6A0074 can connect directly with this. in this case, port e, rs, r/w and db4 - db7 need to interface each other. the transfer is performed by two times. example of timing sequence is shown below. rs r/w e internal signal db7 d7 busy no busy d7 internal operation instruction busy flag check busy flag check instruction d3 ac3 d3 ac3 fig 12. example of 4 - bit bus mode timing sequence
34com/80seg driver & controller for dot matrix lcd S6A0074 43 interface with mpu i n serial mode when im port input is "low ", serial interface mode is started. at this time, all three ports, sclk (synchronizing transfer clock), sid (serial input data), and sod (serial output data), are used. if you want to use S6A0074 with other chips, chip select port (cs) can be used. by set ting cs to "low", S6A0074 can receive sclk input. if cs is set to "high", S6A0074 reset the internal transfer counter. before transfer real data, start byte has to be transferred. it is composed of succeeding 5 "high" bits, read write control bit (r/w), r egister selection bit (rs), and end bit that indicates the end of start byte. whenever succeeding 5 "high" bits are detected by S6A0074, it makes serial transfer counter reset and ready to receive next information. the next input data are register selectio n bit that determine which register will be used, and read write control bit that determine the direction of data. then end bit is transferred, which must have "low" value to show the end of start byte (refer to fig 13. fig 14). write operation (r/w = 0) a fter start byte is transferred from mpu to S6A0074, 8 - bit data is transferred which is divided into 2 bytes, each byte has 4 bit's real data and 4 bit's partition token data. for example, if real data is "10110001" (d0 - d7), then serially transferred data becomes "1011 0000 0001 0000" where 2nd and 4th 4 bits must be "0000" for safe transfer. to transfer several bytes continuously without changing rs bit and rw bit, start byte transfer is needed only at first starting time. namely, after first start byte i s transferred, real data can be transferred succeeding. read operation (r/w = 1) after start byte is transferred to S6A0074, mpu can receive 8 - bit data through the sod port at a time from the lsb. wait time is needed to insert between start byte and data reading, because internal reading from ram requires some delay. continuous data reading is possible like serial write operation. it also needs only one start bytes, only if you insert some delay between reading operations of each byte. during the reading o peration, S6A0074 observes succeeding 5 "high" from mpu. if it is detected, S6A0074 restarts serial operation at once and ready to receive rs bit. so in continuous reading operation, sid port must be "0".
S6A0074 34com/80seg driver & controller for dot matrix lcd 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 r/w rs 0 d0 d1 d2 d3 "0" "0" "0" "0" d4 d5 d6 d7 "0" "0" "0" "0" "1" "1" "1" "1" "1" starting byte synchronizing bit string instruction lower data upper data 1'st byte 2'nd byte cs (input) sclk (input) sid (input) serial write operation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rs d0 d1 d2 d3 "0" "0" "0" "0" "1" "1" "1" "1" "1" starting byte synchronizing bit string busy flag/ read data lower data cs (input) sclk (input) sid (input) serial read operation r/w "0" "0" "0" "0" "0" d4 d5 d6 d7 upper data sod (output) figure 13. timing diagra m of serial data transfer
34com/80seg driver & controller for dot matrix lcd S6A0074 45 start byte 1'st byte 2'nd byte 1'st byte 2'nd byte instruction1 instruction2 instruction3 instruction1 execution time instruction2 execution time instruction3 execution time sclk sid continuous write operation instruction1 execution time instruction2 execution time instruction3 execution time sclk sid continuous read operation start byte data read3 data read2 data read1 wait wait wait wait wait sod 1'st byte 2'nd byte figure 14. timing diagram of continuous data transfer
S6A0074 34com/80seg driver & controller for dot matrix lcd 46 application informat ion according to lcd panel lcd panel: 32 character 1 - line format (5 - dot font, 1/17 duty) S6A0074 com1 com2 com3 com4 com5 com6 com7 com8 com17 (com0) seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg78 seg79 seg80 com16 com15 com14 com13 com12 com11 com10 com9 a lcd panel: 32 character 2 - line format (5 - dot font, 1/33 duty) S6A0074 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 com21 com22 com23 com24 seg1 seg2 seg3 seg78 seg79 seg80 com32 com31 com30 com29 com28 com33 (com0) seg4 seg5 com27 com26 com25 com16 com15 com14 com13 com12 com11 com10 com9
34com/80seg driver & controller for dot matrix lcd S6A0074 47 lcd panel: 16 character x 4 - line format (5 - dot font, 1/33 duty) S6A0074 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 seg1 seg2 seg3 seg78 seg79 seg80 com32 com31 com30 com29 com28 com33 (com0) seg4 seg5 com27 com26 com25 com17 com18 com19 com20 com21 com22 com23 com24
S6A0074 34com/80seg driver & controller for dot matrix lcd 48 lcd panel: 13 charac ter x 4 - line format (6 - dot font, 1/33 duty) S6A0074 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 seg1 seg2 seg3 seg76 seg77 seg78 com32 com31 com30 com29 com28 com33 (com0) seg4 seg5 com27 com26 com25 com17 com18 com19 com20 com21 com22 com23 com24 seg6 seg79 seg80 open open
34com/80seg driver & controller for dot matrix lcd S6A0074 49 initializing initializing by inte rnal reset circuit when the power is turned on, S6A0074 is initialized automatically by power on reset circuit. during the initialization, the followin g instructions are executed, and bf (busy flag) is kept "high"(busy state) to the end of initialization. display clear instruction write "20h" to all ddram set functions instruction dl = 1: 8 - bit bus mode n = 1: 2 - line display mode re = 0: extension regis ter disable be = 0: cgram/segram blink off dh = 0: horizontal scroll enable rev = 0: normal display (not reversed display) control display on/off instruction d = 0: display off c = 0: cursor off b = 0: blink off set entry mode instruction i/d = 1: increm ent by 1 s = 0: no entire display shift bid = 0: normal direction segment port set extension function instruction fw = 0: 5 - dot font width character display b/w = 0: normal cursor (8th line) nw = 0: not 4 - line display mode, 2 - line mode is set because of n("1") enable shift instruction hs = 0000: scroll per line disable ds = 0000: shift per line disable set scroll quantity instruction sq = 000000: not scroll initializing by hard ware reset input when reset pin = "low", S6A0074 can be initialized like the case of power on reset. during the power on reset operation, this pin is ignored.
S6A0074 34com/80seg driver & controller for dot matrix lcd 50 initializing by inst ruction 8 - bit interface mode power on wait for more than 20ms after v dd rises to 4.5v wait for more than 30ms after v dd rises to 2.7v rs r/w db7 db6 db5 db4 db3 db2 db1 db0 function set 0 0 0 0 1 dl(1) n 0 x x wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display on/off control 0 0 0 0 0 0 1 d c b wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 clear display 0 0 0 0 0 0 0 0 0 1 wait for more than 1.53 sms rs r/w db7 db6 db5 db4 db3 db2 db1 db0 entry mode set 0 0 0 0 0 0 0 1 i/d s initialization end dl 0 1 4-bit interface 8-bit interface n 0 1 1-line mode 2-line mode d 0 1 display off display on c 0 1 cursor off cursor on b 0 1 blink off blink on i/d 0 1 decrement mode increment mode s 0 1 entire shift off entire shift on condition: fosc = 270khz (dl = "1")
34com/80seg driver & controller for dot matrix lcd S6A0074 51 4 - bit interface mode power on wait for more than 20ms after v dd rises to 4.5v wait for more than 30ms after v dd rises to 2.7v rs r/w db7 db6 db5 db4 db3 db2 db1 db0 function set 0 0 0 0 1 0 x x x x wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display on/off control wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display clear wait for more than 1.53 ms rs r/w db7 db6 db5 db4 db3 db2 db1 db0 entry mode set initialization end n 0 1 1-line mode 2-line mode dl 0 1 4-bit interface 8-bit interface d 0 1 display off display on c 0 1 cursor off cursor on b 0 1 blink off blink on i/d 0 1 decrement mode increment mode s 0 1 entire shift off entire shift on 0 0 n x x x x x x x 0 0 0 0 0 0 x x x x 0 0 1 d c b x x x x 0 0 0 0 0 0 x x x x 0 0 0 1 i/d sh x x x x 0 0 0 0 0 0 x x x x 0 0 0 0 0 1 x x x x condition: fosc = 270khz rs r/w db7 db6 db5 db4 db3 db2 db1 db0 function set 0 0 0 0 1 dl(0) x x x x wait for more than 39 m s (dl = "0")
S6A0074 34com/80seg driver & controller for dot matrix lcd 52 example of instructi on and display corre spondenc e ie = "low" 1. power supply on: initialized by the internal power on reset circuit rs r/w db7 db6 db5 db4 db3 db2 db1 db0 lcd display 2. function set: 8-bit, 1-line, re(0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 1 0 0 x x 3. display on/off control: display/cursor on rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 1 1 0 _ 4. entry mode set: increment rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 1 0 s _ 5. write data to ddram: write s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 1 0 0 1 1 _ 6. write data to ddram: write a rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 0 0 0 0 1 sa _ 7. write data to ddram: write m rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 0 1 1 0 1 sam _ 8. write data to ddram: write s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 1 0 0 1 1 sams _
34com/80seg driver & controller for dot matrix lcd S6A0074 53 9. write data to ddram: write u rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 lcd display samsu_ 0 0 1 0 1 0 1 0 1 10. write data to ddram: write n rs r/w db7 db6 db5 db4 db3 db2 db1 db0 11. write data to ddram: write g rs r/w db7 db6 db5 db4 db3 db2 db1 db0 12. cursor or display shift: cursor shift to right rs r/w db7 db6 db5 db4 db3 db2 db1 db0 13. entry mode set: entire display shift enable rs r/w db7 db6 db5 db4 db3 db2 db1 db0 14. write data to ddram: write k rs r/w db7 db6 db5 db4 db3 db2 db1 db0 15. write data to ddram: write s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 16. write data to ddram: write 0 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 1 x x 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 samsun_ samsung_ samsung _ amsung k_ msung ks_ sung ks0_ samsung _
S6A0074 34com/80seg driver & controller for dot matrix lcd 54 17. write data to ddram: write 0 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 lcd display ung ks00_ 0 0 0 1 1 0 0 0 0 18. write data to ddram: write 7 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 19. write data to ddram: write 3 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 20. cursor or display shift: cursor shift left rs r/w db7 db6 db5 db4 db3 db2 db1 db0 21. write data to ddram: write 4 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 22. return home rs r/w db7 db6 db5 db4 db3 db2 db1 db0 23. clear display rs r/w db7 db6 db5 db4 db3 db2 db1 db0 ng ks007_ g ks007 4_ ks0074_ s amsung ks0074 _ 1 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 0 0 x x 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 x 0 0 0 0 0 0 0 0 0 1 g ks007 4
34com/80seg driver & controller for dot matrix lcd S6A0074 5 5 ie = "high" 1. power supply on: initialized by the internal power on reset circuit rs r/w db7 db6 db5 db4 db3 db2 db1 db0 2. function set: 8-bit, re(1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 3. extended function set: 5-font, 4-line rs r/w db7 db6 db5 db4 db3 db2 db1 db0 4. function set: re(0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 5. display on/off control: display/cursor on rs r/w db7 db6 db5 db4 db3 db2 db1 db0 6. write data to ddram: write s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 1 _ s_
S6A0074 34com/80seg driver & controller for dot matrix lcd 56 7. write data to ddram: write a rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 sa_ 0 0 1 0 0 0 0 0 1 12. write data to ddram: write g rs r/w db7 db6 db5 db4 db3 db2 db1 db0 13. set ddram address 20h rs r/w db7 db6 db5 db4 db3 db2 db1 db0 14. write data to ddram: write k rs r/w db7 db6 db5 db4 db3 db2 db1 db0 19. write data to ddram: write 4 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 20. set ddram address 40h rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 1 1 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 samsung_ samsung _ samsung k_ samsung ks0074_ samsung ks0074 _
34com/80seg driver & controller for dot matrix lcd S6A0074 57 21. write data to ddram: write l rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 samsung ks0074 l_ 0 0 1 0 0 1 1 0 0 30. write data to ddram: write r rs r/w db7 db6 db5 db4 db3 db2 db1 db0 31. set ddram address 60h rs r/w db7 db6 db5 db4 db3 db2 db1 db0 43. write data to ddram: write r rs r/w db7 db6 db5 db4 db3 db2 db1 db0 44. function set: re("0"), dh("1") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 45. function set: re("1") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 samsung ks0074 lcd driver_ samsung ks0074 lcd driver _ samsung ks0074 lcd driver & controller_ samsung ks0074 lcd driver & controller_ samsung ks0074 lcd driver & controller_
S6A0074 34com/80seg driver & controller for dot matrix lcd 58 46. shift/scroll enable: ds4("1"), ds3/2/1("0") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 samsung ks0074 lcd driver & controller_ 0 0 0 0 1 1 0 0 0 47. function set: re("0") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 48. cursor or display shift: display shift to left rs r/w db7 db6 db5 db4 db3 db2 db1 db0 49. cursor or display shift: display shift to left rs r/w db7 db6 db5 db4 db3 db2 db1 db0 50. cursor or display shift: display shift to left rs r/w db7 db6 db5 db4 db3 db2 db1 db0 51. cursor or display shift: display shift to left rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 1 1 0 x x 0 0 0 0 0 1 1 0 x x 0 0 0 0 0 1 1 0 x x 0 0 0 0 0 1 1 0 x x samsung ks0074 lcd driver & controller_ samsung ks0074 lcd driver controller_ samsung ks0074 lcd driver controller_ samsung ks0074 lcd driver ontroller_ samsung ks0074 lcd driver ntroller_
34com/80seg driver & controller for dot matrix lcd S6A0074 59 52. return home rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 s amsung ks0074 lcd driver & controller 0 0 0 0 0 0 0 1 x 53. function set: re("0), rev("1") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 54. cursor or display shift: display shift to right rs r/w db7 db6 db5 db4 db3 db2 db1 db0 55. cursor or display shift: display shift to right rs r/w db7 db6 db5 db4 db3 db2 db1 db0 56. return home rs r/w db7 db6 db5 db4 db3 db2 db1 db0 57. function set: re("0"), rev("0") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 1 1 1 x x 0 0 0 0 0 1 1 1 x x 0 0 0 0 0 0 0 0 1 x 0 0 0 0 1 1 1 0 0 0 s amsung ks0074 lcd driver & controller s amsung ks0074 lcd driver & controller s amsung ks0074 lcd driver & controller s amsung ks0074 lcd driver & controller s amsung ks0074 lcd driver & controller
S6A0074 34com/80seg driver & controller for dot matrix lcd 60 58. function set: re("1") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 s amsung ks0074 lcd driver & controller 0 0 0 1 1 1 1 0 0 59. entry mode set: bid("1") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 60. clear display rs r/w db7 db6 db5 db4 db3 db2 db1 db0 61. write data to ddram: write b rs r/w db7 db6 db5 db4 db3 db2 db1 db0 62. write data to ddram: write i rs r/w db7 db6 db5 db4 db3 db2 db1 db0 63. write data for ddram: write d rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 0 _
34com/80seg driver & controller for dot matrix lcd S6A0074 61 frame frequency 1/17 duty cycle ... ... 17 16 3 2 1 17 16 4 3 2 1 1-line selection period vdd v1 v4 v5 . . com1 1 frame 1 frame item display font width 5 - dot font width 6 - dot font width 1 - line selection period 200 clocks 240 clocks frame frequency 79.4hz 66.2hz fosc = 270khz (1 clock = 3.7 m s) 1/33 duty cycle ... ... 33 32 3 2 1 33 32 4 3 2 1 1-line selection period vdd v1 v4 v5 . . com1 1 frame 1 frame item display font width 5 - dot font width 6 - dot font width 1 - line selection period 100 clocks 120 clocks frame frequency 81.8hz 68.2hz fosc = 270khz (1 clock = 3.7 m s)
S6A0074 34com/80seg driver & controller for dot matrix lcd 62 power supply for dri ving lcd panel when an external pow er supply is used vdd v1 v2 v3 v4 v5 vdd r r r r vee r0 when an internal boo ster is used vdd v1 v2 v3 v4 v5 vdd r r r r r0 v ci gnd c1 c2 v5out2 v5out3 can be detached if not using power down mode 1 m f + - 1 m f + - + - boosting twice vdd v1 v2 v3 v4 v5 vdd r r r r r0 v ci gnd c1 c2 v5out2 v5out3 can be detached if not using power down mode 1 m f + - 1 m f + - + - boosting three times 1 m f + - boosted output voltage should not exceed the maximum value (13 v) of the lc d driving voltage. especially, a voltage of over 4.3v should not be input to the reference voltage (vci) when boosting three times. a voltage of over 5.5v should not be input to the reference voltage (vci) when boosting t wice. the value of resistance, according to the number of lines, duty ratio and the bias, is shown below. (refer to table 13)
34com/80seg driver & controller for dot matrix lcd S6A0074 63 table 13. duty ratio and power supply for lcd driving item data number of lines 1 2 or 4 duty ratio 1/17 1/33 bias 1/5 1/6.7 divided resistance r r r r0 r 2.7r maximum absolute rat e characteristic symbol value unit power supply voltage (1) v dd - 0.3 to +7.0 v power supply voltage (2) v lcd v dd - 15.0 to v dd +0.3 v input voltage v in - 0.3 to v dd +0.3 v operating temperature t opr - 30 to +85 c storage temperature t stg - 55 to +125 c voltage greater than above may damage to the circuit (vdd 3 v1 3 v2 3 v3 3 v4 3 v5)
S6A0074 34com/80seg driver & controller for dot matrix lcd 64 electrical character istics dc characteristics ( vdd = 2.7v to 5.5v, t a = - 30 to +85 c) characteristic symbol condition min typ max unit operating voltage v dd - 2.7 - 5.5 v supply current i dd internal oscillation or external clock. (v dd = 3.0v, fosc = 270khz - 0.15 0.3 ma input voltage (1) (except osc1) v ih1 - 0.7v dd - v dd - v il1 v dd = 2.7 - 3.0 - 0.3 - 0.2v dd v dd = 3.0 - 5.5 - 0.3 - 0.6 input voltage (2) (osc1) v ih2 - 0.7v dd - v dd v v il2 - - - 0.2v dd output voltage (1) (db0 - db7) v oh1 i oh = - 0.1ma 0.75v dd - - v v ol1 i ol = 0.1 ma - - 0.2v dd output voltage(2) (exce pt db0 - db7) v oh2 i o = - 40 m a 0.8v dd - - v v ol1 i o = 40 m a - - 0.2v dd voltage drop vd com i o = 0.1ma - - 1 v vd seg - - 1 input leakage current i lkg v in = 0v - v dd - 1 - 1 m a low input current i il v in = 0v, v dd = 3v (pull up) - 10 - 50 - 120 internal clock (external rf) f osc rf = 91k w 2% (v dd = 5v) 190 270 350 khz external clock f ec 125 270 410 k hz duty - 45 50 55 % t r , t f - - 0.2 m s voltage converter out2 (vci = 4.5v) v out2 ta = 25 c, c = 1 m f, i out = 0.25ma, - 3.0 - 4.2 - v voltage converter out3 (vc i = 2.7v) v out3 f osc = 270khz - 4.3 - 5.1 - voltage converter input vci - 1.0 - 4.5 v lcd driving voltage v lcd v dd - v5 1/5 bias 3.0 - 13.0 1/6.7 bias 3.0 - 13.0
34com/80seg driver & controller for dot matrix lcd S6A0074 65 ac characteristics (vdd = 4.5 to 5.5v, t a = - 30 to +85 c ) table 14. ac characteristics mode item symbol min typ max unit (1) write mode e cycle time tc, 500 - - ns (refer to figure 15) e rise/fall time tr, tf - - 20 e pulse width (high, low) tw 230 - - r/w and rs setup time tsu1 40 - - r/w and rs hol d time th1 10 - - data setup time tsu2 60 - - data hold time th2 10 - - (2) read mode (refer to figure 16) e cycle time tc 500 - - ns e rise/fall time tr, tf - - 20 e pulse width (high, low) tw 230 - - r/w and rs setup time tsu 40 - - r /w and rs hold time th 10 - - data output delay time t d - - 160 data hold time t dh 5 - - (3) serial interface serial clock cycle time tc 0.5 - 20 m s mode serial clock rise/fall time tr, tf - - 50 ns (refer to figure 17) serial clock width (high, low) tw 200 - - chip select setup time tsu1 60 - - chip select hold time th1 20 - - serial input data setup time tsu2 100 - - serial input data hold time th2 100 - - serial output data delay time t d - - 160 serial output data hold time t dh 5 - -
S6A0074 34com/80seg driver & controller for dot matrix lcd 66 table 14. ac characteristics (continued) (vdd = 2.7 to 4 .5v, t a = - 30 to +85 c) mode item symbol min typ max unit (4) write mode e cycle time tc, 1000 - - (refer to figure 15) e rise/fall time tr, tf - - 25 e pulse width (high, low) tw 450 - - r/w and rs setup time tsu1 60 - - r/w and rs hold time th1 20 - - data setup time tsu2 195 - - data hold time th2 10 - - ns (5) read mode e cycle time tc 1000 - - (refer t o figure 16) e rise/fall time tr, tf - - 25 e pulse width (high, low) tw 450 - - r/w and rs setup time tsu 60 - - r/w and rs hold time th 20 - - data output delay time t d - - 360 data hold time t dh 5 - - n s (6) serial interface serial clock cycle time tc 1 - 20 m s mode serial clock rise/fall time tr, tf - - 50 ns (refer to figure 17) serial clock width (high, low) tw 400 - - chip select setup time tsu1 60 - - chip select hold time th1 20 - - serial i nput data setup time tsu2 200 - - serial input data hold time th2 200 - - serial output data delay time t d - - 360 serial output data hold time t dh 5 - -
34com/80seg driver & controller for dot matrix lcd S6A0074 67 v ih1 v il1 t su1 v il1 t h1 v il1 t h1 t f t w t h2 v ih1 v il1 t su2 t r v ih1 v il1 valid data v ih1 v il1 t c db0 - db7 e r/w rs v il1 v ih1 v il1 figure 15. write mode v ih1 v il1 t su v ih1 t h v ih1 t h t f t w t dh v ih1 v il1 t r v oh1 v ol1 valid data v oh1 v ol1 t c db0 - db7 e r/w rs t d v il1 v ih1 v il1 figure 16 . read mode
S6A0074 34com/80seg driver & controller for dot matrix lcd 68 v il1 t su1 t h1 sod sid sclk cs v ih1 v il1 t w t w t c t r v ih1 v il1 v ih1 v il1 v ih1 v il1 t dh v oh1 v ol1 t d t su2 t h2 tf v il1 figure 17. serial interface mode reset timing (vdd = 2.7 to 5.5v, t a = - 30 to +85 c) item symbol min typ max unit reset low level width (refer to figure 18) t res 10 - - ms reset v il1 v il1 t res figure 18. reset timing diagram

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